A MTJ is a key component in MRAM, spin-torque MRAM, and other spintronic devices and comprises a stack with a tunnel barrier layer such as a metal oxide formed between two magnetic layers that provides a tunneling magnetoresistance (TMR) effect. One of the magnetic layers is a free layer and serves as a sensing layer by switching the direction of its magnetic moment in response to external fields while the second magnetic layer has a magnetic moment that is fixed and functions as a reference layer. The electrical resistance through the tunnel barrier layer (insulator layer) varies with the relative orientation of the free layer moment compared with the reference layer moment and thereby provides an electrical signal that is representative of a magnetic state in the free layer. In a MRAM, the MTJ is formed between a top conductor and bottom conductor. When a current is passed through the MTJ, a lower resistance is detected when the magnetization directions of the free and reference layers are in a parallel state and a higher resistance is noted when they are in an anti-parallel state. Since MTJ elements are often integrated in CMOS devices, the MTJ must be able to withstand annealing temperatures around 400° C. for about 30 minutes that are commonly applied to improve the quality of the CMOS units for semiconductor purposes.
MTJ elements wherein the free layer (FL) and reference layer (RL) have perpendicular magnetic anisotropy (PMA) are preferred over their counterparts that employ in-plane anisotropy because a PMA-MTJ has an advantage in a lower writing current for the same thermal stability, and better scalability. In MTJs with PMA, the FL has two preferred magnetization orientations that are perpendicular to the physical plane of the layer. Without external influence, the magnetic moment of the free layer will align to one of the preferred two directions, representing information “1” or “0” in the binary system. For memory applications, the FL magnetization direction is expected to be maintained during a read operation and idle, but change to the opposite direction during a write operation if the new information to store differs from its current memory state. CoFeB or the like is commonly used as the FL and RL, and MgO is preferred as the tunnel barrier to generate PMA along the RL/MgO and MgO/FL interfaces in a RL/MgO/FL stack.
Spin-torque (STT)-MRAM based technologies are desirable for nonvolatile memory applications. However, realizing low critical dimensions below 100 nm that match those found in Dynamic Random Access Memory (DRAM) is a challenge. MTJs are highly susceptible to sidewall damage, both chemical and physical, induced by etching and deposition processes, and exacerbated by the CMOS process requirement of annealing at 400° C.
During fabrication of a conventional STT-MRAM device where a dielectric layer is deposited on MTJ sidewalls in order to insulate the MTJ from adjacent MTJ devices in the STT-MRAM array, damage frequently occurs to the MTJ sidewalls. Damage may result from oxygen diffusion through a MTJ sidewall during an oxide dielectric layer deposition, for example, and thereby oxidize a significant portion of the MTJ. In some cases, metal from a MTJ capping layer may be redeposited on MTJ sidewalls to cause shunting around the tunnel barrier layer, or electrical short circuits. As a result, there is a reduction in device performance, substantial non-uniformity between bits that translates into an undesirable larger distribution of key metrics, and lower device yields. Reducing sidewall damage is especially important at the CoFeB/MgO (RL/tunnel barrier and tunnel barrier/FL) interfaces that generate interfacial PMA. Furthermore, the delicate nature of the MgO tunnel barrier layer is well known to have poor corrosion properties and readily degrades when exposed to atmosphere during deposition of the insulating dielectric layer.
Although methods are available to remove sidewall damage caused by ion bombardment, and by exposure to atmosphere during dielectric layer deposition, the methods are generally time consuming and costly. Moreover, some sidewall damage may be too extensive to repair. There is a need to prevent MTJ sidewall damage by providing a means of protecting a MTJ element during subsequent process steps in memory device fabrication.